Non-volatile memories are extensively used for storing data in processing systems. Examples include erasable programmable read-only memories (EPROM), electrically erasable programmable read-only memories (EEPROM), and Flash memory. These memories are typically internally arranged such that memory cells form arrays consisting of rows and columns. The rows and columns have decode blocks associated therewith, so that any one cell can be uniquely specified.
For programming purposes, non-volatile memories generally have bitlines for carrying data through the array in one dimension. For example, a common technique in memory design is to have bitlines traverse the array in the "Y" direction, such that each cell in a column shares the same bitline during programming. The bitlines are commonly driven during programming by program latches which have been loaded with the desired data prior to programming the memory cells. The number of program latches generally corresponds to the number of columns in the array.
Program latches are generally loaded a subset at a time, with the size of the subset being constrained by the width of the data bus external to the integrated circuit. For example, in a typical device having an 8 bit wide external data bus, but having 256 program latches internal to the device, 32 load operations of 8 bits each are required to load all 256 program latches prior to a programming operation. One well known method of loading a subset of the latches is to provide decoding circuitry that selects the subset to be loaded and de-selects the subset not to be loaded, thereby only asserting control signals corresponding to the set to be loaded. This decoding circuitry consumes space on the integrated circuit.
It is desirable to minimize the size of the program latches in part because when less space is consumed by the latches, more space is available for other circuitry for any given die size. One recognized method of reducing the size of program latches is to do away with the decoding circuitry so that all program latches receive the same "load" signal, and then only driving the input data lines of the data latches to be loaded, and to let the remaining data input lines float. This approach, however, creates a new set of problems, including the problem that the capacitance of the floating data input lines can present a substantial load to the inputs of the latches not intended for loading. If the capacitive load is great enough, charge is "shared" between the capacitive load on the input data line and the input of the latch to the extent that the logic sense of the latch input can be upset, thereby modifying the latch contents in error. This "charge sharing" is undesirable.
For the reasons stated above, and for other reasons stated be low which will become apparent to those skilled in the art up on reading and understanding the present specification, there is a need in the art for a method and apparatus to provide immunity from charge sharing in latch designs.